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Etude d'un processeur RISC pour un système symbolique parallèle = A study of a RISC processor for a parallel symbolic systemJemai, Abderrazak; Berger-Sabbatel, Gilles.1992, 146 p.Thesis

Second-generation RISC floating point with multiply-add fusedHOKENEK, E; MONTOYE, R. K; COOK, P. W et al.IEEE journal of solid-state circuits. 1990, Vol 25, Num 5, pp 1207-1213, issn 0018-9200, 7 p.Article

NStrace : A bus-driven instruction trace tool for PowerPC microprocessorsSANDON, P. A; LIAO, Y.-C; COOK, T. E et al.IBM journal of research and development. 1997, Vol 41, Num 3, pp 331-344, issn 0018-8646Conference Paper

Le microprocesseur F-RISC: architecture haut niveau et environnement de programmation = The F-RISC microprocessor: high level architecture and programming environmentDelorme, Vincent; Mehrez, H.1994, 134 p.Thesis

Design of high-integration microcontroller for consumer Internet applicationsMILNE, G; ELBRO, P; JOHNSON, J et al.IEEE transactions on consumer electronics. 1997, Vol 43, Num 4, pp 1070-1073, issn 0098-3063Article

Parallelism and the ARM instruction set socs architectureGOODACRE, John; SLOSS, Andrew N.Computer (Long Beach, CA). 2005, Vol 38, Num 7, pp 42-50, issn 0018-9162, 9 p.Article

Instruction scheduling with timing constraints on a single RISC processor with 0/1 latenciesHUI WU; JAFFAR, Joxan; YAP, Roland et al.Lecture notes in computer science. 2000, pp 457-469, issn 0302-9743, isbn 3-540-41053-8Conference Paper

A multimedia RISC core for efficient bitstream parsing and VLDBEREKOVIC, M; MEYER, G; YONG GUO et al.SPIE proceedings series. 1998, pp 131-141, isbn 0-8194-2751-9Conference Paper

Performance simulation analysis of RISC-based multiprocessors under uniform and nonuniform trafficOBAIDAT, M. S.Information sciences. 1993, Vol 72, Num 1-2, pp 157-177, issn 0020-0255Article

The decoupled-style prefetch architectureRICH, K. D; FARRENS, M. K.Lecture notes in computer science. 2000, pp 989-993, issn 0302-9743, isbn 3-540-67956-1Conference Paper

Fast implementation of elliptic curve defined over GF(pm) on CalmRISC with MAC2424 coprocessorJAE WOOK CHUNG; SANG GYOO SIM; PIL JOONG LEE et al.Lecture notes in computer science. 2000, pp 57-70, issn 0302-9743, isbn 3-540-41455-XConference Paper

Parallel RISC Architecture. A Functional Approach Based on Backus's FP languageMALITA, Mihaela; STEFAN, Gheorghe M.Parallel and distributed processing techniques and applications. International conferenceWorldComp'2011. 2011, pp 492-498, isbn 1-60132-193-7 1-60132-194-5 1-60132-195-3, 7 p.Conference Paper

Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode SupportVASSILIADIS, Nikolaos; THEODORIDIS, George; NIKOLAIDIS, Spiridon et al.Lecture notes in computer science. 2006, pp 217-229, issn 0302-9743, isbn 3-540-36708-X, 1Vol, 13 p.Conference Paper

POEtic : A prototyping platform for bio-inspired hardwareMORENO, J. Manuel; THOMA, Yann; SANCHEZ, Eduardo et al.Lecture notes in computer science. 2005, pp 177-187, issn 0302-9743, isbn 3-540-28736-1, 11 p.Conference Paper

An SoC with two multimedia DSPs and a RISC core for video compression applicationsSTOLBERG, H.-J; MOCH, S; FRIEBE, L et al.IEEE International Solid-State Circuits Conference. 2004, pp 330-331, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

Cycle-accurate energy model and source-independent characterization methodology for embedded processorsSYED SAIF ABRAR.International Conference on Embedded Systems DesignInternational Conference on VLSI Design. 2004, pp 749-752, isbn 0-7695-2072-3, 1Vol, 4 p.Conference Paper

Validating word-oriented processors for bit and Multi-word operationsLEE, Ruby B; XIAO YANG; SHI, Zhijie Jerry et al.Lecture notes in computer science. 2004, pp 473-488, issn 0302-9743, isbn 3-540-23003-3, 16 p.Conference Paper

Design and development of a new POD module chip-set based on the OpenCable specificationKIM, Won Hee; SONG, Won Jay; KIM, Bo Gwan et al.Interantional conference on consumer electronics. 2002, pp 208-209, isbn 0-7803-7300-6, 2 p.Conference Paper

A methodology for the formal analysis of asynchronous micropipelinesCERONE, Antonio; MILNE, George J.Lecture notes in computer science. 2000, pp 246-262, issn 0302-9743, isbn 3-540-41219-0Conference Paper

A risc-style hardware accelerator for operating systemsDJORDJEVIC, J; BOJOVIC, M; TOMASEVIC, M et al.International journal of computers & applications. 1999, Vol 21, Num 2, pp 50-55, issn 1206-212XArticle

Performance estimation of embedded software with pipeline and cache hazard modelingIMLIG, N; TSUTSUI, A.Lecture notes in computer science. 1997, pp 131-142, issn 0302-9743, isbn 3-540-63766-4Conference Paper

Gras: a general framework for combining automatic code generation and register allocationBRYANT, K. S; MAUNEY, J.Computer languages. 1995, Vol 21, Num 2, pp 101-112, issn 0096-0551Article

Expression-tree-based algorithms for code compression on embedded RISC architecturesARAUJO, Guido; CENTODUCATTE, Paulo; AZEVEDO, Rodolfo et al.IEEE transactions on very large scale integration (VLSI) systems. 2000, Vol 8, Num 5, pp 530-533, issn 1063-8210Conference Paper

Self modifying circuitry : A platform for tractable virtual circuitryDONLIN, A.Lecture notes in computer science. 1998, pp 199-208, issn 0302-9743, isbn 3-540-64948-4Conference Paper

The architecture of a highly reconfigurable RISC dataflow array processorSAIT, S. M; FAROOQUI, A. A.International journal of electronics. 1997, Vol 83, Num 4, pp 493-518, issn 0020-7217Article

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